The invention relates to plasma etch processes used in the manufacture of semiconductor integrated circuits. In particular, the invention relates to an in situ integrated process for etching layered dielectric structures serving as inter-level dielectric layers.
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices which can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being developed which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon, such as silicon dioxide, silica glass such as BPSG, and related silicon-based oxide materials that serve as electrical insulators. Recently, interest has developed in insulating materials with low dielectric constants (low-k dielectrics), some of which are based upon silicon but others are based upon carbon.
Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, require several layers of metallization with intervening inter-level dielectric layers. Small contact or via holes need to be etched through each of the dielectric layers. The contact or via holes are then filled with a conductor, composed typically of aluminum in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the contact or via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual-damascene structure, as illustrated in sectioned orthographic view in FIG. 1, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual-damascene processes, self-aligned and counterbore, both of which produce the structure of FIG. 1.
A substrate 10 includes a conductive feature 11 in its surface. If the substrate 10 already includes a wiring level at its surface, the conductive feature 11 is metallic and may be a previously formed dual-damascene metallization. The interconnection between two metallic wiring levels is called a via. Conventionally, the metal forming the metallization has been aluminum and its alloys, but advanced integrated circuits are being designed with copper metallization. Alternatively, the conductive feature 11 may be a doped region in a silicon substrate 10, for example, a source or drain. In this case, the interconnection between the silicon layer and a first metallization layer is called a contact. Although some aspects of the present invention apply to contacts, the major portion of the disclosure and the details of the invention are directed to vias, particularly copper vias and underlying copper lines 11.
Over the substrate 10 and the included conductive feature 11 are deposited a lower stop layer 12, a lower dielectric layer 14, an upper stop layer 16, and an upper dielectric layer 20. The stop layers 12, 16 have compositions relative to those of the dielectric layers 14, 20 such that an etch chemistry is available which effectively etches a vertical hole in the overlying dielectric layer 14, 20 but stops on the stop layer 12, 16. That is, the etch selectively etches the dielectric layer over the stop layer. Alternatively stated, the dielectric etch is selective to the stop material. As mentioned before, more advanced circuits are being designed with the two dielectric layers 14, 16 being composed of a dielectric material having a lower dielectric constant than that of silicon dioxide. However, the specific examples of the invention use silicon dioxide, related non-stoichiometric materials SiOx, and related silica glasses for the dielectric. Some related glasses are borophosphosilicate glass (BPSG) and fluorinated silica glass (FSG), which exhibit much the same chemistry as SiO2. These materials will be hereafter collectively be referred to as oxides. The typical stop material for oxide is silicon nitride (Si3N4) although non-stoichiometric ratios SiNx, are included where x may be between 1.0 and 1.5. These materials will hereafter be referred to as nitrides. An advantage of the combination of oxide and nitride is that the both materials can be grown in a single reactor by plasma-enhanced chemical vapor deposition (PECVD). For example, silicon dioxide is grown under PECVD using tetraorthosilicate (TEOS) as the main precursor gas. Silicon nitride can be grown in the same reactor using silane as the main precursor in the presence of a nitrogen plasma. These examples are non-limiting and simply show the advantage of the vertical structure.
The dual-damascene etch structure shown in FIG. 1 is formed in the previously described vertical structure. The discussion with respect to the invention will disclose at least one way of performing the dual-damascene etch. The result is that a generally circular via hole 18 is etched through the lower oxide layer 14 and the lower nitride stop layer 12 to reach the underlying conductive feature 11. Multiple such via holes 18 are etched to reach different ones of the conductive features 11. A trench 22 extending along the surface of the substrate 10 is etched through at least the upper oxide layer 20 and usually through the upper nitride stop layer 16.
After completion of the dual-damascene etch structure of FIG. 1, the trench 22 and vias 18 are filled with a metal such as aluminum or copper. Physical vapor deposition (PVD) is the usual process for depositing the metal though it may be combined with chemical vapor deposition (CVD) or replaced by electro or electroless plating. Barrier layers are usually first conformally coated in the hole being filled. A typical barrier for copper includes Ta/TaN. The metal is deposited to a thickness that overfills the trench 22 and also covers a top planar surface 30 of the upper oxide layer 30. Chemical mechanical polishing (CMP) is applied to the top surface of the wafer. CMP removes the relatively soft exposed metal but stops on the relatively hard oxide layer 20. The result is a horizontal metal interconnect within the trench 22 and multiple vertical metal interconnects (vias) in the via holes 18.
In the past, equipment limitations have required the frequent transfer of a semiconductor integrated circuit wafer being process from one vacuum processing chamber to another. Exposure of the wafers to the air environment during the transfer between vacuum chambers often results in corrosion of the metal features of the partially processed integrated circuit. The well known susceptibility of copper to corrosion in air increases the destructive risk. Also, carbon-based residue that forms on the interior of the reactor chamber over time can redeposit on exposed copper surfaces. Since these carbon based residues can be extremely difficult to remove from copper, their presence can adversely impact upon subsequent formation of electrical contacts to the copper.
Tang et al. and Hung et al. in the previously cited patent applications, incorporated herein by reference in their entireties, disclose an integrated counterbore process for etching the dual-damascene structure of FIG. 1. The process is particularly advantageous because it can be performed in a single etch reactor, such as the inductive plasma source (IPS) etch reactor available from Applied Materials of Santa Clara, Calif. This reactor is illustrative of a new class of inductively coupled plasma reactors that are capable of generating a high-density plasma (HDP) and which separate the generation of the plasma from the biasing of the pedestal supporting the wafer. Such a reactor provides both the selectivity and the process flexibility required to satisfy the conflicting requirements of the many steps of an integrated in situ process. There are other types of high-density plasma reactors, including remote plasma source (RPS) and electron-cyclotron resonance (ECR). A high-density plasma may be defined as a plasma filling the entire space it is in, excluding plasma sheaths, and having an ionization density of at least 1011 cmxe2x88x923.
Collins et al. have described the IPS etch reactor in U.S. patent application Ser. No. 08/733,554, filed Oct. 21, 1996. The general reactor structure and some auxiliary equipment are illustrated in partial cross section in FIG. 2. A wafer 40 to be processed is supported on a cathode pedestal 42, which is supplied with RF power from a first RF power supply 44. A silicon ring 46 surrounds the pedestal 42 and is controllably heated by an array of heater lamps 48. A grounded silicon wall 50 surrounds the plasma processing area. A silicon roof 52 overlies the plasma processing area, and lamps 54 and water cooling channels 56 control its temperature. The temperature-controlled silicon ring 86 and to a lesser extent the silicon roof 52 can be used to scavenge fluorine from the fluorocarbon or other fluorine-based plasma. Processing gas is supplied from one or more bottom gas feeds 54 through a bank of mass flow controllers 56. Alternatively, a top gas feed may be formed as a small showerhead in the center of the silicon roof 52. An unillustrated vacuum pumping system connected to a pumping channel 58 around the lower portion of the chamber maintains the interior of the chamber at a preselected pressure. A system controller 60 controls the operation of the reactor and its auxiliary equipment.
In the used configuration, the silicon roof 52 is grounded, but its semiconductor resistivity and thickness are chosen to pass generally axial RF magnetic fields produced by an inner inductive coil stack 66 and an outer inductive coil stack 68 powered by respective RF power supplies 70, 72. Alternatively, a single RF power supply may be used in conjunction with a selectable power splitter. Other coil configurations are possible, for example, as in the TCP reactor having a flat, spiral inductive coil overlying the roof 52.
The system controller 60 controls the mass flow controllers 56, the heater lamps 48, 54, the supply of chilled water to the cooling channels 56, the throttle valve to the vacuum pumps, and the power supplies 44, 70, 72. All these regulated functions control the etching chemistry in conformance to a process recipe of the sort to be described in the examples below. The process recipe is stored in the controller 60 in magnetic, optical, or semiconductor memory, as is well known in the art, and the controller 60 reads the recipe from a recording medium inserted into it. It is typical for the equipment supplier to provide recipes on magnetic media such as floppy disks or optical media such as CDROMs, which are then read into controller 60.
A principal advantage of the inductively coupled plasma reactor is that different amounts of power can be supplied to the inductive coils 66, 68 and to the capacitive pedestal 42. The inductive power creates a plasma source region located in large part remotely from the wafer 40 while the capacitive power controls the plasma sheath adjacent to the wafer 40 and thus determines the DC bias across the sheath at the wafer 40. The source power can be raised to increase the etching rate and control the number and type of excited radicals while the bias power can be varied to cause ions to be accelerated across the plasma sheath with either high or low energy and which then strike the wafer 40 with the selected energy.
The integrated counterbore dual-damascene etch process of Tung et al. and Hung et al. as practiced in the IPS reactor is summarized in FIG. 3. In step 74, all the dual-damascene layers 12, 14, 16, 20 are grown in a horizontally unpatterned vertical structure. All the layers can be grown in a single CVD chamber by sequentially changing gas flows, power levels, and other reactor parameters. In step 76, a photoresist layer is deposited over the upper oxide layer 20 and patterned with apertures corresponding to the via holes 18.
In step 78, an extended via hole is etched from the top of the upper oxide layer 20 to the top of the lower nitride stop layer 12. Because the counterbore via etch 78 must etch through the upper nitride stop layer 16 but stop on the lower nitride stop layer 12, a multi-step via etch is required. Tang et al. disclose both a two-substep and a three-substep via etch step 74. The parameters for the two-substep via etch are given in TABLE 1.
The counterbore via etch is demanding because it must etch very deeply, for example, 2.5 xcexcm through a very narrow hole. A hole width of no more than 0.25 xcexcm is required, and a width of 0.18 xcexcm and less is being contemplated. These very high aspect ratios mean that etch stop is a problem. Etch stop arises from the fact that the high selectivity of fluorocarbon-based oxide etches to underlying silicon or silicon nitride as well as verticality of the side walls depend upon a polymer depositing on non-oxide surfaces and on the side walls. However, if the etching chemistry is too rich (favoring too much polymer formation), the polymer bridges the sidewalls and covers the oxide bottom of the developing hole and prevents further etching. The final step of the counterbore via etch also requires good selectivity to the underlying lower nitride stop layer 12. The use of CO in the first step reduces selectivity to nitride, thus allowing the upper nitride stop layer 16 to be etched.
An alternative three-step etch of Tang et al., particularly applicable to a wider geometry is summarized in TABLE 2.
It begins with an oxide etch selective to nitride that goes no further than the upper nitride stop layer. The second step is less selective to nitride, allowing the upper nitride stop layer to be etched through. The third step is again selective to nitride so it etches through the lower oxide layer and stops on the lower nitride stop layer. This process allows tighter control on where the different steps begin and end.
At the completion of the via etch sequence, the wafer is removed from the etch reactor, and in step 80 a photoresist layer is deposited over the top of the upper oxide layer 30 and patterned to the area of the trench 22. The wafer is returned to the same or another IPS reactor.
In a trench etch step 82, the upper oxide layer 20 is etched down to the upper nitride stop layer 16, thereby forming the trench 22. After the trench etch 82, a post etch treatment 84 is used in the IPS chamber to remove any remaining photoresist and any polymer produced in the trench etch 82. This step is sometimes referred to as ashing. Finally, in a nitride removal step 86, the lower nitride layer 12 exposed at the bottom of the via hole 18 is removed.
Hung et al. give an example of the three steps 82, 84, 86, as summarized in TABLE 3.
In the trench etch step 82, a fluorocarbon-based etch is used to etch the upper oxide layer 20 but to stop on the upper nitride stop layer 16. The trench etch is not prone to etch stop because of the relatively open trench geometry. However, the trench etch must be very selective to nitride because the lower nitride stop layer 12 is exposed to the entire duration of the trench etch. Selectivity of oxide over nitride is achieved by the combination of a fluorocarbon chemistry and a relatively high bias power producing energetic ions for reactive ion etching. The relatively high ring temperature and low wafer temperature also foster good selectivity. If the lower nitride stop layer 12 were to be punched through in the trench etch, the relatively high ion energies used to achieve oxide-to-nitride selectivity would sputter the copper thus exposed in the underlying copper metallization 11. The copper would redeposit on the sidewalls of the via hole 18 and significantly degrade the electric characteristics of the inter-level oxide. Note that in copper PVD, barrier layers are deposited in the via hole 18 and trench 22 prior to the copper deposition to prevent the copper from migrating into the oxide.
The post etch treatment 84 uses an oxygen-based plasma at relatively low bias power, typically less than 20% of that used in the selective etch. The nitride removal 82 uses a combination of a fluorocarbon and an oxygen component at similarly low bias power to reduce the selectivity to nitride. The low bias power prevents significant sputtering of the exposed copper.
Both the counterbore via etch of Tang et al. and the trench etch of Hung et al. are respective in situ processes performable in a single reactor without removing the wafer from the reactor. Such an in situ process greatly increases through put because less wafer transfer is required and thermal and significant pressure ramps are not required between the substeps. Nonetheless, the process produces good structural characteristics.
However, further work has revealed some shortcomings of the processes described above and need for further capabilities.
The photolithography required for features of size approximately 0.25 xcexcm and smaller is extremely demanding since even the far ultraviolet light used in advanced lithography has a wavelength not much different from this dimension, and photoresist thicknesses tend to be even greater to achieve good light absorption. Unless the photolithographic light is well coupled into the photoresist layer, standing waves may be set up in the photoresist layer. Thin photoresist layers may be used that are patterned by scanned electron beams, but e-beams are not considered amendable to high-volume production. Therefore, for the desired smaller feature sizes, it becomes necessary to apply an anti-reflective coating (ARC) between the top of the dielectric layers and beneath the photoresist. Two types of anti-reflective coatings are common. A dielectric anti-reflective coating (DARC) is composed of silicon oxynitride and may be deposited in the same plasma-enhanced CVD reactor as the other layers in the dual-damascene stack. A bottom anti-reflection coating (BARC) is a carbonaceous polymer similar to photoresist that begins as an organic suspension that is spun onto the wafer as a very thin layer and dried to form the polymeric layer having an advantageous refractive index. An example of BARC is BARLi, available from Hoechst Celanese. The integrated process needs to include the opening of the ARC layer in one or both of the etch steps.
Typically in the prior art, after a wafer has been subjected to a complete plasma etching step, it is wet cleaned with a commercially available cleaning solvent such as EKC for aluminum or ACT for copper to remove polymeric and other residues prior to the next step of lithography, PVD, or CVD. Although wet cleaning is relatively effective at providing clean surfaces for the next step, it is a slow and labor-intensive process inconsistent with the trend to automated, clean-room processing. It is thus desirable to substitute for the wet clean a final plasma clean in the integrated etch process.
The final nitride removal step of Hung et al. has been observed to side etch the lower nitride stop layer and thus to undercut the lower oxide layer. Such undercutting is not desirable. It is difficult for the conformal sputtering barrier layer to fill such small lateral recess, and if copper does fill it, the underlying oxide is unprotected. If the recess leaves voids in the PVD deposited metal, reliability is reduced.
The invention may be summarized as an in situ integrated etch process for etching oxide and other inter-level dielectrics. The process may be performed in a single chamber for all the necessary etching substeps in one level of etching, for example, including opening an anti-reflective coating and doing a final plasma clean as well as etching the dielectric and stop layer. The invention is particularly useful when a dielectric layer is underlaid with a stop layer, for example, an oxide dielectric and a nitride stop.
The invention is particularly applicable to a dual-damascene etch requiring two photolithographic steps and concomitant etching steps. A counterbore via etch etches a via hole through two levels of dielectric and an intervening stop layer but stops on the lower stop layer. A subsequent trench etch etches a larger feature in the upper dielectric layer and also includes a final stop removal and post-etch treatment. Oxide and nitride are the preferred materials for the dielectric and stop.
An aspect of the invention includes after the principal dielectric etch a first post-etch treatment, a stop removal step, and a subsequent short second post-etch treatment. This is especially important when a copper metallization is being exposed beneath the stop layer.